Intel's Meteor Lake and the chiplet revolution

Intel’s Meteor Lake processor is built from four separate chips, packaged together on a single substrate. A compute tile, a graphics tile, a SoC tile, and an I/O tile. Four chips, potentially manufactured on four different process nodes, assembled into one product.

This is called chiplet architecture. And I think it’s the most important change in chip design in decades.

The economics

A traditional chip is monolithic. Everything on one piece of silicon. CPU cores, GPU, memory controller, I/O, all fabricated on the same process node, cut from the same wafer.

The problem: leading-edge process nodes (3nm, 5nm) are absurdly expensive. A single wafer processed on TSMC’s 3nm node costs roughly $20,000. If your chip is big, you get fewer chips per wafer. If a single defect ruins the whole chip, your yield drops. Big chips on expensive nodes are a recipe for cost explosions.

Chiplets solve this by splitting the chip into smaller pieces. The CPU cores (which need the fastest node for performance) go on 3nm. The I/O controller (which doesn’t need bleeding-fast speed) goes on a cheaper node, maybe 6nm or even 16nm. The memory controller goes on whatever node makes sense for its requirements.

Each chiplet is smaller. Smaller chips mean more chips per wafer. More chips per wafer means better yield economics. And because each chiplet uses the node appropriate for its function, you’re not paying for 3nm where you don’t need 3nm.

It’s modular thinking applied to silicon. And it changes the math of chip manufacturing fundamentally.

AMD got there first

AMD pioneered chiplet CPUs with their Zen 2 architecture in 2019. They separated the CPU cores (small “CCD” chiplets on TSMC’s 7nm) from the I/O die (a larger chip on an older 12nm node). The result was competitive performance at lower cost than Intel’s monolithic designs.

AMD proved the concept works. Intel is now following, and extending it further. Meteor Lake uses Intel’s Foveros 3D packaging, which stacks chiplets vertically in addition to placing them side by side. More integration in less area.

What it means

The chiplet revolution means the semiconductor industry can keep improving even when the individual transistors are nearing physical limits. You don’t need to shrink everything to 2nm. You need to shrink the parts that benefit from it and use cheaper, mature nodes for everything else.

This is a subtle but profound shift. For 60 years, the story of chips was: make the transistors smaller. That story is approaching its physical limits. The new story is: make the packaging smarter. Combine different chips, from different fabs, on different nodes, into a product that’s better than any single chip could be.

IEEE Spectrum called it “the Lego approach to chip design.” I like that analogy. Instead of sculpting a chip from a single block of silicon, you assemble it from standardized building blocks.

The implications cascade. Smaller companies can design chiplets without needing access to the most expensive fabs. Different chiplets from different vendors can potentially be mixed and matched. The supply chain becomes more distributed, which has geopolitical benefits too.

Meteor Lake is Intel catching up to AMD’s approach. But the broader trend is bigger than either company. Chiplets are how the industry keeps Moore’s Law alive, not by making transistors smaller, but by making chips smarter.

That shift is worth paying attention to.

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