TSMC's 2nm process and the question of what

TSMC announced production details for its N2 process. Two nanometers. I’ve been writing about chip manufacturing for six years and the numbers still make my brain stutter.

Two nanometers is roughly 10 silicon atoms across. Ten. If a transistor were a building, each floor would be a single atom. And TSMC is building billions of these on a wafer the size of a dinner plate, with defect rates low enough to mass-produce.

The engineering is extraordinary. But the physics are starting to push back.

Where we are

Moore’s Law, the observation that transistor density doubles roughly every two years, has been the metronome of the computing industry since 1965. It’s not a law of physics. It’s a statement about human ingenuity: we keep finding ways to make transistors smaller and cheaper.

At 2nm, the “smaller” part is running into quantum mechanics. Electrons at this scale don’t behave like tiny balls rolling down tiny channels. They tunnel through barriers. They exist probabilistically. The laws that govern them are wave equations, not Newtonian mechanics.

Every process node from here gets exponentially harder. Not just “engineering challenge” harder. “Fundamental physics” harder. The transistor architecture had to change from planar to FinFET at 22nm because the old approach stopped working. Now it’s changing again from FinFET to Gate-All-Around at 2nm, because FinFETs can’t control leakage currents at these scales.

ASML’s High-NA EUV machines, which cost over $350 million each, are needed for the next steps. The light used to pattern these chips has a wavelength of 13.5nm, and they’re using it to print features at 2nm. That’s like using a paintbrush 7 times wider than what you’re painting to paint precise lines. The optical engineering required is staggering.

The wall

There is a wall. Maybe not at 2nm. Maybe not at 1nm. But somewhere between here and atomic-scale transistors, shrinking stops working.

IBM Research has demonstrated transistors at sub-1nm dimensions in the lab. But lab demonstrations and mass production are separated by a chasm of yield engineering, reliability testing, and economic viability. Building one transistor at 0.5nm and building 100 billion of them on a single chip with 99.99% yield are different achievements by many orders of magnitude.

IEEE Spectrum published a thoughtful piece about the options beyond silicon shrinking. The alternatives are not hypothetical. They’re in labs today.

Carbon nanotube transistors. Carbon nanotubes can carry more current at smaller dimensions than silicon. MIT built a functioning computer from carbon nanotube processors in 2019. The challenge is manufacturing: growing billions of identical nanotubes, aligned perfectly, is something nobody can do reliably yet.

Photonic computing. Using light instead of electrons to process information. Light moves faster, generates less heat, and doesn’t suffer from the same quantum effects at small scales. Photonic chips for specific workloads (like AI inference) are already in production from companies like Lightmatter.

3D chip stacking. Instead of making transistors smaller, stack more layers of transistors vertically. TSMC and Intel are both investing heavily in this. The challenge is heat dissipation: each layer generates heat, and the layers below can’t dissipate it easily.

Quantum computing. For specific problem types (optimization, simulation, cryptography), quantum gates operate on fundamentally different principles that sidestep the limitations of classical transistors entirely.

What I think happens

I don’t think silicon goes away. I think it stops being the only material. The chips of 2035 will probably be hybrid: silicon for general computation, carbon nanotubes for high-performance logic, photonic interconnects for data movement, and maybe a quantum module for specific workloads. All on the same package, IMEC-style heterogeneous integration.

The post-silicon era isn’t one material replacing another. It’s multiple materials, each used where its physics work best, assembled into something more capable than any single approach could achieve.

That’s more complex than the last 60 years of chip design. It requires a new kind of chip architect. Someone who understands silicon, carbon, photonics, and quantum physics. The specialization that drove the industry for decades gives way to integration that demands breadth.

The 10-atom meditation

I keep going back to the 10 atoms. Ten atoms wide. We’re building structures at the scale where individual atoms matter. Where removing one atom from a transistor changes its behavior.

Humans started working with matter at the scale of rocks and logs. We refined it to bricks and beams. Then to gears and springs. Then to wires and circuits. Now to atoms.

Each step down in scale required a new understanding of physics. Newtonian mechanics gave way to materials science gave way to semiconductor physics gave way to quantum mechanics. Each transition felt like a wall until someone figured out the door.

I don’t know what the door past 2nm looks like. I don’t think anyone does, not fully. But I’ve been watching this industry for long enough to know that “the wall” and “the wall we actually hit” are usually different walls. The one we worry about turns out to have a side path. The one we didn’t see coming is the real obstacle.

Ten atoms. It’s wild that we can build anything at that scale. It’ll be wilder to see what we build when that scale isn’t enough anymore.

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